Serializer/deserializer (“SERDES”) devices are frequently used in high-speed communication networks in which an interface must be provided between parallel bus-connected devices and high-speed serial communication networks, such as those implemented through optical fiber interconnections. For these applications, a system (such as a computer processor and related devices) writes in parallel to a plurality of First-In First-Out memories or registers (“FIFOs”), with each write cycle based on a system clock, and with each FIFO corresponding to one of the parallel data channels or data paths. In turn, a SERDES device will read from each such parallel FIFO, with each read cycle based on a SERDES clock, and convert the parallel data into serial data, such as for serial data transmission.
Because such write and read operations are based on different clocks which are not synphase with each other, data alignment issues arise, in which data content of a selected channel may be misaligned or skewed with respect to data content of another selected channel. As a consequence, a data alignment or data synchronization signal, such as a “comma” signal in various data transmission and data bus standards, is utilized to provide alignment among the various data channels.
In current systems, upon the occurrence of such a comma, write pointers are advanced to the first comma location of one of the channels, so that all FIFOs or channels are then written to simultaneously in the next write cycle. Such current alignment systems, however, provide for potentially overwriting data and the transmission of potentially corrupted data.
As a consequence, a need remains for a multichannel data alignment or data synchronization apparatus, system and method which provides for accurate data alignment, while minimizing the potential for data overwriting and transmission of corrupted data.